Verification Engineer - UVM/System Verilog

Location: Hyderabad Experience: 6+ Years Work Mode: Onsite 5 Days a Week Shift: Regular Education: B.E./B.Tech/M.E./M.Tech Interview Process: 2 Rounds R1 Virtual, R2 F2F/Virtual Role Overview: We are looking for an experienced Verification Engineer with 6+ years of hands-on experience in Functional Verification, with strong expertise in SystemVerilog and UVM. The candidate will be responsible for developing and executing coverage-driven verification environments and ensuring high-quality verification of complex designs/IPs. Top 3 Skills: - Functional Verification 6+ years of hands-on experience - SystemVerilog - UVM Key Responsibilities: - Develop and execute functional verification environments using SystemVerilog and UVM. - Create and maintain UVM-based testbenches, test scenarios, sequences, drivers, monitors and scoreboards. - Implement coverage-driven verification strategies to achieve functional and code coverage goals. - Develop and debug SystemVerilog Assertions (SVA). - Analyze simulation failures, identify root causes and drive issues to closure. - Work with design and verification teams to resolve functional and RTL-related issues. - Use industry-standard simulators such as Questa or VCS. - Contribute to verification planning, test development, regression execution and coverage analysis. Required Skills: - 6+ years of hands-on experience in Functional Verification. - Strong expertise in SystemVerilog and UVM. - Good experience with Functional Coverage, Assertions (SVA) and Coverage-Driven Verification. - Strong debugging and problem-solving skills. - Hands-on experience with Questa and/or VCS simulators. Preferred / Nice-to-Have Skills: - Experience with MIPI protocols. - Experience with DDR4/DDR5. - Knowledge of AMBA protocols, including AXI4, AXI4-Lite and AXI4-Stream. - Familiarity with VIP-based verification environments. - Exposure to FPGA/Vivado-based IP verification flows.