Sr. Manager - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine Learning

AWS Utility Computing (UC) provides product innovations — from foundational services such as Amazon’s Simple Storage Service (S3) and Amazon Elastic Compute Cloud (EC2), to consistently released new product - 7+ years of ASIC implementation, synthesis, STA and physical design in deep sub-micron nodes (16nm or smaller) experience - 7+ years of digital design in communication systems experience - 7+ years of full-custom analog or RF layout experience - 7+ years of wireless communications systems and implementation experience - 8+ years of creating and maintaining automation frameworks for Post-Silicon Flow experience - 7+ years of verification in communication systems experience - 5+ years of UVM, C, System C, and scripting experience - 3+ years of emulation experience - Bachelor's degree in Electrical Engineering or a related field - Knowledge of UVM and Matlab - Knowledge of implementing chips with multiple power islands and power gating - Knowledge of multiple access systems including OFDMA, TDMA, and CDMA - Knowledge of end-to-end network system architecture from wireless physical layer to application endpoints - Knowledge of serial protocols including SPI, I2C, I3C, and UART - Knowledge of Python and Embedded C programming - Experience in communication theory, OFDM, MIMO, Digital/Wireless Communication Systems or RF engineering - Experience with current and upcoming RF standards in cellular (4G/5G), WiMAX, 802.

11ad, microwave backhaul, DVB-S2 / DVB-C, or related broadband wireless standards - Experience leading or solely developing methodology and scripts for physical synthesis - Experience taping out chips that have gone into high volume production - Experience developing products for volume production - Experience low power design techniques - Experience delivering products to volume production - Experience in modem L1/L2 algorithms development and architectures - Experience in developing link and system level simulators using MATLAB, Python, or C++ - Experience in test setup automation using MATLAB, Python, or Pearl - Experience with Agile, TDD, BDD, CI, and Git - Experience developing PHY/MAC layer HW/SW targeting SoCs, FPGAs, and general-purpose processors - Experience leading technical initiatives and key deliverables - Experience with version control systems and CI/CD pipeline implementation - Experience in Bare Metal Environment development, including linker scripts, page tables and NVIC - BS + 8yrs or MS + 6yrs or PhD + 4yr in EE/CS - Expertise in timing analysis fundamentals - 3+ years doing Static Timing Analysis - 3+ years with timing constraint development - Timing Analysis using EDA tools (examples: PrimeTime, Tempus, or others) - Understanding of ASIC Physical Design from RTL-to-GDSII - Understanding of other sign-off activities (ir/em, physical verification, DFT)