Sr. Manager, Foundation IP (Standard Cells & Memories),, Annapurna Labs

Annapurna Labs, our silicon organization within AWS Utility Computing, builds the custom chips behind AWS — Graviton, Nitro, Inferentia and Trainium. Our Machine Learning Acceleration (MLA) team develops - 3+ years of people management, managing engineers experience -

• BS in Electrical or Computer Engineering with 12+ years, MS with 10+ years, or PhD with 7+ years of experience in standard cell, memory or custom digital circuit design -

• Hands-on transistor-level design experience across standard cells, sequentials/latches, and SRAM or register files in FinFET or GAA technologies at 5nm or below -

• Experience as the technical interface to foundation IP vendors or foundries — specifying deliverables and driving SOWs, schedules, ECOs and IP quality -

• Experience evaluating standard cell library and memory PPA using block-level synthesis and place-and-route -

• Experience with standard cell and memory characterization and EDA views (Liberty/LVF, LEF, Verilog) using Synopsys PrimeLib/SiliconSmart or Cadence Liberate -

• Proficiency with custom design and verification tools: Cadence Virtuoso or Synopsys Custom Compiler; Spectre or HSPICE/PrimeSim; Siemens Calibre or Synopsys ICV -

• Scripting experience in Python, Tcl, Perl or SKILL