Senior ASIC Design Infrastructure & Methodologies engineer, MLA-MI - Annapurna Labs

Our Machine Learning Acceleration (MLA) team designs and develops the SOCs that power today's AI workloads across datacenters worldwide.

As an ASIC Design Methodologies and Infrastructure Engineer, you'll - 7+ years of ASIC implementation, synthesis, STA and physical design in deep sub-micron nodes (16nm or smaller) experience - 7+ years of digital design in communication systems experience - 7+ years of full-custom analog or RF layout experience - 7+ years of wireless communications systems and implementation experience - 8+ years of creating and maintaining automation frameworks for Post-Silicon Flow experience - 7+ years of verification in communication systems experience - 5+ years of UVM, C, System C, and scripting experience