Senior/Staff Design Verification Engineer - Zero-Defect

A leading technology company in Singapore is seeking a design verification engineer to enhance their verification methodologies. You will join a team focused on achieving zero-defects within complex verification scenarios, utilizing UVM and systems emulation. Ideal candidates should have a background in Electrical Engineering or Computer Engineering and experience in UVM verification methodology. Candidates with strong programming skills and experience in video processing will be preferred. Fresh graduates with strong academic performance are encouraged to apply. #J-18808-Ljbffr