DFT Architect

About Eximietas: Eximietas is a technology company headquartered in San Jose, CA with a global footprint that extends to Bangalore, Chennai and Bhubaneswar in India. Eximietas Design is a leading technology firm specializing in VLSI, Cloud Computing, Cyber Security, AI, and ML solutions. With a commitment to innovation and excellence, we empower businesses to thrive in the dynamic digital landscape. This job might be for you if: - You enjoy solving problems and love taking on difficult challenges. - You don't know the answer but will dig until you find it. - You communicate clearly and write well. - You are motivated, driven, and take ownership of your work. - You can impress our customers with your enthusiasm to solve their issues. Job Description: DFT Architect / Principal DFT Engineer: As a DFT Architect, you will be responsible for defining the comprehensive test strategy, methodology, and architecture for our next-generation, high-performance SoCs and IPs. You will bridge the gap between architectural concepts, RTL design, physical implementation, and post-silicon manufacturing. Key Responsibilities: - Architecture & Strategy: Define and document the end-to-end DFT architecture for large-scale, advanced-node SoCs. - Methodology Development: Establish state-of-the-art DFT methodologies across Scan/ATPG, Memory BIST (MBIST), Logic BIST (LBIST), and Analog/Mixed-Signal test structures. - Standards Enforcement: Lead the implementation of industry-standard test protocols, including IEEE 1149.1 (JTAG), IEEE 1500, and IEEE 1687 (IJTAG). - Cost & Efficiency Optimization: Drive strategies to optimize Test Time (TAT) and Test Data Volume (TDV). - Cross-Functional Collaboration: Partner closely with Frontend Design, Architecture, Physical Design, and Product/Test Engineering teams. - Tool Evaluation: Evaluate, deploy, and benchmark industry-leading EDA tools (Synopsys, Siemens/Mentor, Cadence). - Post-Silicon Support: Lead post-silicon bring-up, ATE pattern validation, and failure analysis/debug. Required Technical Skills: - Education: Bachelor's / Master's / Ph.D. degree in Electrical, Electronics, or Computer Engineering. - Experience: Hands-on experience in DFT design, architecture, and verification. - ATPG Expertise: Deep understanding of ATPG, pattern generation, and advanced fault models. - BIST Solutions: Extensive experience with MBIST insertion, memory self-repair (BISR), and Logic BIST (LBIST). - Hierarchical Flows: Proven track record with hierarchical DFT structures and top-level integration. - EDA Tools: High proficiency with Siemens Tessent, Synopsys TestMax, or Cadence Modus. - Timing & Constraints: Strong baseline in Static Timing Analysis (STA) for DFT/Scan modes. - Scripting: Expert automation skills using Tcl, Perl, Python, or Shell scripting. Preferred Qualifications: - Experience with Automotive Safety Standards (ISO 26262). - Experience architecting DFT for advanced packaging technologies (2.5D / 3D ICs, Chiplets). - Strong understanding of ATE tester architectures. Soft Skills: - Strong leadership qualities with the ability to mentor junior engineers. - Excellent technical documentation and presentation skills. - Problem-solving mindset with an capability to thrive under tight production deadlines.