Lead Engineer - RTL Design, Front End

GlobalFoundries is looking for highly motivated Test Chip Architect for Foundational IP's in the Global Organization, based in Bangalore. The successful candidate will work with 100% quality and minimal cycle time in mind. This role requires a close working relationship and collaboration with internal IP teams, technology, test and product engineering teams. The roles and responsibilities will include architecture definition and design of Test Chips and also Post Silicon Debug till Silicon Report Generation Activities. Your Job: • Well versed in Verilog and SV with good understanding of RTL design, verification and synthesis practices. Prior work experience in the RTL and or gate level verification domain is a must. • Well conversant with different verification methodologies like assertion, function and test coverage with good understanding of test generation process. • Experience in Synthesis / Understanding of timing concepts is a plus. • Knowledge on low power design and verification methods • Expertise in RTL quality sign-off through lint checks, IP to SoC integration, IP hand-off, constraints etc., RTL hand-off to backend. • An expert user of one or more of the following verification tools: NC-Sim*, Modelsim*, VCS, Specman*, Debussy* andor Verdi* • Developing design, verification and validation tools and flows, Work with the verification engineers to help on the verification strategies and participate in test plan and coverage reviews • Analytical problem solving and troubleshooting skills (e.g., LEC debugging, Functional simulation debugging, Script debugging ) • Mentor less experienced design engineers in implementation tasks to ensure compliance to specification, quality standards, and milestones • Should have knowledge of JTAG, SPI, SoC clocking/reset architecture. • Proactive, creative, curious, motivated to learn and contribute with good collaboration skills. Required Qualifications: • Requires Master's Degree (MS/MTech) or Bachelor's Degree with Specialization in Computer Engineering or Electrical (VLSI, Microelectronics and related fields) from a reputed university. • B.S. + minimum of 12 years of relevant experience/M.S. + minimum of 10 years of relevant experience/PhD + minimum of 8 years of relevant experience • Minimum of 10 - 12 years of experience with SOC Design (RTL to GDS) and simulation • Applicant should have a proficient knowledge of and experience with EDA (Cadence, Mentor Graphics, Synopsys…) tools for Front End and Back End design & simulations (DC/Genus, ICC2/Innovus , Virtuoso, Spectre, HSPICE, etc.) • Experience in RTL Coding and Verification, Place and Route and SignOff EMIR, STA and PV • Experience in NVM Memory (MTPM/OTP/MRAM/SRAM/eFlash) designs • Must have good technical verbal and written communication skills and ability to work with cross functional teams • Be able to collaborate with program and technical design leads on multiple concurrent projects. Preferred Qualifications:  • Knowledge in various technologies (Bulk, CMOS & SOI) process is desired • Experience in Silicon debug and design validation is a plus • Patents and publications will be a good advantage • Exceptional Spoken and Written Proficiency in English  • Strong analytical and problem-solving skills.  • Strong ability to learn and explore new technologies, opportunities, and continuous improvement. • Ability to interact effectively with both external and internal customers at all levels and from various cultural backgrounds. Skills: Verilog, Gds, NC sim, NC Verilog, RTL, SOC design Experience: 10.00-18.00 Years