Package Layout Design Engineer , Annapurna Labs - AI Silicon Packaging

Annapurna Labs (our organization within AWS) designs silicon and software that accelerates innovation.

Customers choose us to create cloud solutions that solve challenges that were unimaginable a short - Bachelor's degree in Electrical Engineering or a related field - Experience identifying bugs in architecture, algorithms, functionality, and performance with strong overall debugging skills - Experience verifying at multiple levels of logic from IP blocks to SoCs to full system testing - 5+ years of experience in IC package layout and physical design - Experience executing package designs from concept through tape out for multi-layer organic substrates or silicon interposers - Hands-on experience with package layout tools such as Cadence APD/SiP, Synopsys IC Packaging, Mentor Xpedition, or equivalent - Understanding of advanced packaging technologies: 2.

5D/3D-IC, fan-out WLP, RDL, TSV, microbump, or silicon bridge interconnects - Working knowledge of package design rules, DFM constraints, and physical verification methodologies (DRC, connectivity checks) - Experience with bump map and ball map definition, escape routing strategies, and power/ground plane design - Good communication skills with the ability to work effectively across design, SI/PI, and manufacturing teams