Job Description
Job Details Job Description: Join us as a CPU DFD (Design-For-Debug) Validation Engineer and play a pivotal role in shaping the future of next generation of Intel CPU. In this role, you will ensure the reliability and functionality of cutting-edge CPUs by verifying DFD logic designs against specifications, and will develop various debug solutions in the form of software to support in-house post-silicon validation and external customers. This is a unique opportunity to collaborate with industry-leading architects, designers, and engineers to refine and advance Intel's CPU microarchitecture. Key Responsibilities Develop comprehensive DFD verification plans, test benches, and environments to achieve full coverage of DFD functionality against CPU microarchitecture specifications. Define and execute verification plans, run system simulation/emulation/FPGA models, analyze power and timing, and uncover bugs in the design. Develop software solution to support in-house post-silicon validation activities and external customers, and provide necessary post-silicon debug support as needed to internal validation/manufacturing and external customers Replicate, root cause, and debug issues in both pre-silicon and post-silicon environments, implementing corrective actions as needed. Collaborate with CPU architects, RTL developers, and physical design teams to ensure DFD usage models are viable for post-silicon debug usages Document detailed test plans and lead technical reviews with design and architecture teams. Maintain and improve existing functional verification infrastructure and methodologies. Contribute to the definition and development of innovative DFD architecture/microarchitecture features within the CPU design process. Qualifications Minimum Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. 2+ years of experience with a Bachelor's degree / Master's degree, or PhD graduate. Proficiency in System Verilog and U
