Job Description
Position Summary About Samsung Semiconductor India Research (SSIR) With a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more. As one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability high performance and value added services that enable Samsung Electronics deliver world-class products. Role and Responsibilities Roles and Responsibilities . Complete ownership of timing constraint at image sensor full chip and sub system levels. This includes: o Timing constraint (Hierarchical, Flat) development and release for Synthesis/PD work o Timing constraint validation using various EDA tools o Analysis of pre-layout and post-layout timing reports and debug o Incremental update of constraint as and when it is required o Working with RTL,DFT and PD teams independently and driving in timing closure both at sub system and fullchip level. . RTL PPA analysis (physical and power aware) at sub system levels for power, performance, area trade-off. This includes: o Running relevant EDA tool and generate reports o Analysing the reports o Working with RTL , PD teams to improve the quality of RTL and Physical implementation . Development of necessary scripts in TCL, Perl and/or Python for efficiency improvement Required Skill Set: . Strong unders
