Senior FPGA Design Engineer (Int, Sr and Prinicpal)

Design and implement RTL using Verilog and SystemVerilog for complex FPGA systems Translate high-level requirements into detailed architecture and design specifications Execute full FPGA design flow including synthesis, place and route, and timing closure Develop and optimize designs for high-speed, high-performance applications Work across multiple clock domains including asynchronous CDC handling Collaborate with verification teams to ensure functional correctness and coverage Debug and resol…