Job Description
Do you have a passion for invention and self-challenge? Do you thrive on pushing the limits of what's considered feasible. As part of a world class modem team, you'll be at the heart of chip design! Apple recently announced first in-house 5G modem platforms, the C1 and C1X, designed to deliver industry-leading connectivity performance, improved energy efficiency, and seamless integration with Apple's custom silicon. You'll ensure Apple products and services can seamlessly handle the tasks that make them beloved by millions. Join us, and you'll help us innovate new cellular technologies that continually outperform the previous iterations! Do you want to have an impact on every single Apple product? As an ASIC STA engineer, you will be responsible for all aspects of timing including, working with designers for timing constraints generation, helping construct/modify flows, timing analysis and timing closure. Description As an ASIC STA Engineer, you will have responsibilities spanning various aspects of SOC design: Full chip and block level timing closure ownership throughout the entire project. Generation of block and full chip timing constraints. Own timing sign-off to make sure timing requirements are met across all corners, modes, and conditions. Work closely with various multi-functional teams on resolving sophisticated timing issues for major building blocks of complex SoCs. Work on Apple SoC (System-on-Silicon) chips in deep sub-micron technologies targeted for high end mobile applications. Responsibilities: As an STA Engineer, the day-to-day work involves performing static timing analysis across multiple corners and modes using tools like Synopsys PrimeTime. The role includes maintaining and validating SDC constraints, collaborating closely with RTL, synthesis, and physical design teams to resolve timing issues. Own STA sign-off for block and chip level including custom timing checks. Develop automation scripts in Tcl or Python to streamline analysis and reporti
