Job Description
Lead RTL Engineer Location: Austin, TX (Onsite) Key Skills RTL Lead experience Processor/CPU Design Microarchitecture and Architecture Ownership Responsibilities Translate architecture specifications into synthesizable SystemVerilog. Own RTL coding standards, linting rules, and design methodology. Lead a team of 5 to 7 RTL engineers through the full design cycle. Own the synthesis flow using Design Compiler or Genus and drive timing closure. Define and maintain SDC timing constraints. Review al…
